Analog Devices AD9520-5 Clock Generator Datasheet

The AD9520-5 is a low phase noise, phase-locked loop (PLL) that supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz, 1 differential or 2 single-ended reference inputs, accepts CMOS, LVDS or LVPECL references to 250 MHz, accepts 16.67 MHz to 33.3 MHz crystal for reference input, optional reference clock doubler, reference monitoring capability, automatic and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching, glitch-free switchover between references, automatic recovery from holdover, digital or analog lock detect, selectable zero delay operation, 12 1.6 GHz LVPECL outputs divided into 4 groups, each group of 3 has a 1 to 32 divider with phase delay, additive output jitter as low as 225 fs rms, channel-to-channel skew grouped outputs <16 ps, each LVPECL output can be configured as differential or single-ended, and the output frequency and phase offset can be selected.


Analog Devices AD9520-5 Clock Generator Datasheet - cover page
Brand
Analog Devices
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
77
File format
PDF
File size
1.6 MB
Published
24 March, 2012
Updated
30 September, 2023
MD5 checksum
BD3598AE5A4F587B8421AD139E7B7604

About this manual

The AD9520-5 is a multi‑output clock generator offering twelve LVPECL outputs arranged in four groups, each configurable with a 1‑to‑32 divider and phase delay. It supports external VCO/VCXO up to 2.4 GHz, provides low‑jitter performance (as low as 225 fs rms), and includes both digital and analog lock‑detect options.

The device operates from a single 3.3 V supply (VS 3.135‑3.465 V) with optional driver supplies (VS_DRV 2.375‑5.25 V). It accepts a variety of reference inputs (CMOS, LVDS, LVPECL) up to 250 MHz and crystal references from 16.67 MHz to 33.33 MHz. The AD9520-5 is specified for –40 °C to +85 °C operation and includes EEPROM for configuration storage.

What's inside

  • Features
  • Applications
  • General Description
  • Functional Block Diagram
  • Specifications
  • Power Supply Requirements
  • PLL Characteristics
  • Clock Inputs
  • Clock Outputs
  • Timing Characteristics

Specifications

Number of LVPECL outputs12
LVPECL output groups4 groups, each with 1‑to‑32 divider
Maximum LVPECL output frequency2400 MHz
Additive output jitter225 fs rms
Channel‑to‑channel skew (grouped outputs)<16 ps
Supply voltage (VS)3.135 V – 3.465 V
Driver supply voltage (VS_DRV)2.375 V – 5.25 V
Operating temperature range–40 °C to +85 °C
Reference input typesCMOS, LVDS, LVPECL up to 250 MHz
Crystal reference frequency range16.67 MHz – 33.33 MHz

Frequently asked questions

What is the maximum output frequency of the LVPECL outputs?

The LVPECL outputs can reach up to 2400 MHz.

What is the operating temperature range of the AD9520-5?

The device is specified for operation from –40 °C to +85 °C.

How many LVPECL outputs does the AD9520-5 provide?

It provides twelve LVPECL outputs, organized into four groups.

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