The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP) that combines an efficient 16-bit digital signal processing core, program and data memories, multiple peripherals, and system support circuitry on a single semiconductor chip. Unique features of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL), making it a cost-effective, high-performance solution for many DSP applications, especially speech coding, digital communications, and cellular base stations.
The DSP56156 is a general‑purpose 16‑bit digital signal processor with a built‑in sigma‑delta codec and PLL, targeting speech coding, digital communications, and cellular base stations. It offers a highly parallel instruction set, three execution units, and up to six operations per instruction cycle.
This datasheet details the processor’s architecture, memory configuration, pin assignments, package options, and electrical specifications. It also lists related documentation and ordering information for the 112‑pin CQFP and TQFP packages.
| Core | 16‑bit digital signal processing core |
|---|---|
| Maximum Instruction Rate | 30 MIPS |
| Instruction Cycle at 60 MHz | 33 ns |
| Maximum Operation Rate | 180 MOPS at 60 MHz |
| Program RAM | 2048 × 16‑bit |
| Bootstrap ROM | 64 × 16‑bit (or 12 k × 16‑bit on ROM variant) |
| Data RAM | 2048 × 16‑bit |
| Package Options | 112‑pin CQFP (20 × 20 × 3 mm) or TQFP (20 × 20 × 1.5 mm) |
| Power Supply | 5 V |
| General‑Purpose I/O Pins | Up to 27 |
| On‑Chip Codec | Sigma‑delta voice‑band codec (100 kHz‑3 MHz) |
The DSP56156 can execute up to 30 million instructions per second (30 MIPS).
It includes 2048 × 16‑bit on‑chip program RAM.
The device is offered in a 112‑pin Ceramic Quad Flat Pack (CQFP) and a 112‑pin Plastic Thin Quad Flat Pack (TQFP).
Yes, it includes an on‑chip sigma‑delta voice‑band codec with sampling rates from 100 kHz to 3 MHz.