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The DSP56156 is the first member of Motorola's DSP56100 family of HCMOS, low power, 16-bit general purpose Digital Signal Processors (DSP). Designed primarily for speech coding and telecommunications, it features a built-in sigma-delta voice band codec and phase locked loop (PLL). The processor includes memories, digital peripherals, and provides an off-the-shelf solution with no user programmable ROMs on-chip.
The Central Processing Unit consists of three execution units operating in parallel, allowing up to six operations per instruction cycle. It supports fractional and integer arithmetic, nested hardware DO loops, and zero-overhead fast interrupts. The device operates at frequencies down to DC with a single 5V power supply.
| Operating Frequency | 60 MHz |
|---|---|
| Instructions per Second | Up to 30 MIPS |
| Power Supply | Single 5V |
| On-chip Data RAM | 2k x 16-bit |
| On-chip Program RAM | 2k x 16-bit |
| Operating Frequency Range (Codec) | 100KHz to 3MHz |
It is designed primarily for speech coding and telecommunications.
No, it requires no off-chip components.