Datasheet
The HSP9501 is a 10-bit wide programmable data buffer designed for use in high speed digital systems. It has two operating modes, delay mode and recirculate mode. In delay mode, it can provide 2 to 1281 clock cycles of delay. In recirculate mode, it provides a programmable circular buffer. The length of the buffer or amount of delay can be programmed through the LC0-10 length control input port and the LCEN length control enable port.
User Manual
The HSP9501 is a 10-bit wide programmable data buffer designed by Intersil and is used in high speed digital systems. The buffer can be selected to operate in two different modes: delay mode and data recirculate mode. In the delay mode, a programmable data pipeline is created which can provide 2 to 1281 clock cycles of delay between the input and output data. In the data recirculate mode, the output data path is internally routed back to the input to provide a programmable circular buffer. The length of the buffer or amount of delay is programmed through the use of the 11-bit Length Control Input Port (LC0-10) and the Length Control Enable (LCEN). An 11-bit value is applied to the LC0-10 inputs, LCEN is asserted, and the next selected clock edge loads the new count value into the Length Control Register. The delay path of the HSP9501 consists of two registers with a programmable delay RAM between them, therefore, the value programmed into the Length Control Register is the desired length - 2. The range of values which can be programmed into the Length Control Register are from 0 to 1279.
