The HSP9501 is a 10-bit wide programmable data buffer designed for use in high speed digital systems. It has two operating modes, delay mode and recirculate mode. In delay mode, it can provide 2 to 1281 clock cycles of delay. In recirculate mode, it provides a programmable circular buffer. The length of the buffer or amount of delay can be programmed through the LC0-10 length control input port and the LCEN length control enable port.
The HSP9501 is a 10-bit wide programmable data buffer designed for high-speed digital systems. It supports two modes: delay mode for programmable pipeline delays (2 to 1281 clock cycles) and recirculate mode for circular buffering. The buffer length is controlled by an 11-bit Length Control Register, with values from 0 to 1279 resulting in delays from 2 to 1281. Clock select logic allows use of positive or negative edge clocks, and outputs are three-state for bus interfacing. It is suitable for video/image processing, sample rate conversion, and audio data handling.
The device operates from DC to 32MHz, features TTL-compatible I/O, and is low-power CMOS. Pin descriptions and functional timing are detailed, including control inputs for mode selection, clock edge selection, and length programming. Ordering information includes PLCC packages for temperature ranges from 0 to 70°C.
| Operating Frequency | DC to 32MHz |
|---|---|
| Buffer Length | 2 to 1281 words |
| Data Word Width | 10-Bits |
| Clock Edge Selection | Positive or Negative |
| Output Type | Three-State |
| Power Supply | +5V |
| Package Type | 44 Ld PLCC |
The HSP9501 supports both positive and negative edge system clocks via the CLKSEL input.
It is designed for use in high speed digital systems.
Delay mode and data recirculate mode.
1279.