Key facts
- Brand
- Samsung
- Model
- S3C24A0
- Documents
- 2
- Languages
- EN
- Last added
- 2012-04-01
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Samsung S3C24A0 RISC Microprocessor Preliminary Product Overview
The S3C24A0 is a 16/32‑bit ARM926EJ‑S based RISC microprocessor designed for 2.5G/3G mobile phones and embedded applications. It integrates dual‑32‑bit bus architecture, caches, MMU, LCD controller, camera interface, MPEG‑4 video engine and a modem interface.
The document provides detailed specifications of memory subsystems, serial interfaces (UART, USB, SPI, I2C, IIS), video processing blocks, power management registers and mechanical data, targeting hardware designers and system integrators.
Samsung S3C24A0 specifications
| Instruction Cache | 16 KB |
|---|---|
| Data Cache | 16 KB |
| UART Channels | 2 |
| DMA Controllers | 4 channels |
| GPIO Width | 32‑bit |
| Address Space | Up to 1 GB |
| USB Host Specification | OHCI Rev.1.0, USB 1.1 |
| Soft‑reset Command | 0xA3 |
Source: Samsung S3C24A0 RISC Microprocessor Preliminary Product Overview
All Samsung S3C24A0 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the size of the instruction and data caches?
Both the instruction cache and data cache are 16 KB each.
From: Samsung S3C24A0 RISC Microprocessor Preliminary Product Overview
Which USB specifications does the S3C24A0 comply with?
It complies with OHCI Rev. 1.0 and the USB Specification version 1.1.
From: Samsung S3C24A0 RISC Microprocessor Preliminary Product Overview
How many interrupt sources does the S3C24A0 provide?
The processor supports 61 interrupt sources.
From: Samsung S3C24A0 RISC Microprocessor Preliminary Product Overview
What is the cache size and organization of the S3C24A0?
It has a 4‑way set‑associative cache with 16 KB instruction cache and 16 KB data cache.
From: Samsung S3C24A0 RISC Microprocessor Preliminary Product Overview