Samsung S3C24A0 RISC Microprocessor Preliminary Product Overview

s3c24a0 is a application processor developed by samsung electronics for 2.5g/3g mobile phones.


Samsung S3C24A0 RISC Microprocessor Preliminary Product Overview - cover page
Brand
Samsung
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
487
File format
PDF
File size
6.4 MB
Published
01 April, 2012
Updated
30 September, 2023
Model
S3C24A0
MD5 checksum
4F48673E42F016E4492C49B7BA151A10

About this manual

The S3C24A0 is a 16/32‑bit ARM926EJ‑S based RISC microprocessor designed for 2.5G/3G mobile phones and embedded applications. It integrates dual‑32‑bit bus architecture, caches, MMU, LCD controller, camera interface, MPEG‑4 video engine and a modem interface.

The document provides detailed specifications of memory subsystems, serial interfaces (UART, USB, SPI, I2C, IIS), video processing blocks, power management registers and mechanical data, targeting hardware designers and system integrators.

What's inside

  • Introduction
  • Memory Subsystem
  • Serial Communication
  • Video Processing
  • Power Management
  • Peripherals

Specifications

Instruction Cache16 KB
Data Cache16 KB
UART Channels2
DMA Controllers4 channels
GPIO Width32‑bit
Address SpaceUp to 1 GB
USB Host SpecificationOHCI Rev.1.0, USB 1.1
Soft‑reset Command0xA3

Frequently asked questions

What is the size of the instruction and data caches?

Both the instruction cache and data cache are 16 KB each.

Which USB specifications does the S3C24A0 comply with?

It complies with OHCI Rev. 1.0 and the USB Specification version 1.1.

What is the soft‑reset command code for the processor?

The soft‑reset is activated by writing the value 0xA3 to the SOFTRESET register.

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