S3C24A0 is a Samsung 2.5G/3G mobile phone application processor. This document is an introduction to the functions of the processor.
The S3C24A0 is a 16/32‑bit ARM926EJ‑S based RISC microprocessor designed for 2.5G/3G mobile phones and general embedded applications. It features a dual‑32‑bit bus architecture, separate 16 KB instruction and data caches, an MMU, and a rich set of hardware accelerators for video, audio and communications.
The document details the memory subsystem (up to 1 GB address space, dual AHB buses), peripheral blocks such as UART, USB host/device, DMA, timers, watchdog, RTC, GPIO, camera and LCD controllers, as well as power‑management registers and mechanical data. It serves as a preliminary reference for developers evaluating the chip.
| CPU core | ARM926EJ‑S 16/32‑bit RISC |
|---|---|
| Cache configuration | 4‑way set‑associative, 16 KB I‑Cache, 16 KB D‑Cache |
| Interrupt sources | 61 sources |
| DMA controller | 4‑channel |
| UART channels | 2‑channel with DMA support |
| Watchdog timer | 16‑bit |
| RTC clock | 32.768 kHz operation |
| USB host ports | 2‑port USB Host (OHCI 1.0) |
| Display support | Up to 640×480, 320×240, 176×192 resolutions |
The processor supports 61 interrupt sources.
It has a 4‑way set‑associative cache with 16 KB instruction cache and 16 KB data cache.
Yes, it includes a 2‑port USB Host compliant with OHCI Rev. 1.0.
The RTC operates at 32.768 kHz.