National Semiconductor USBN9603 Manuals

We have 6 manuals for the National Semiconductor USBN9603: 5 Datasheets, 1 User Manual. Free to view online or download as PDF.

National Semiconductor USBN9603 manuals

NATIONAL SEMICONDUCTOR USBN9603/USBN9604 Manual

User Manual

USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support is an integrated USB node controller produced by National Semiconductor Corporation.

NATIONAL SEMICONDUCTOR - USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support handbook

Datasheet

The USBN9603/4 are integrated USB Node controllers with enhanced DMA support. They are compatible with USB specification versions 1.0 and 1.1, and are advanced versions of the USBN9602. The devices integrate the required USB transceiver, a 3.3V regulator, a Serial Interface Engine (SIE), USB endpoint (EP) FIFOs, a versatile 8-bit parallel interface, a clock generator, and a MICROWIRE/PLUS™ interface. Seven endpoint pipes are supported: one for the mandatory control endpoint and six to support interrupt, bulk, and isochronous endpoints. Each endpoint pipe has a dedicated FIFO, 8 bytes for the control endpoint and 64 bytes for the other endpoints. The 8-bit parallel interface supports multiplexed and non-multiplexed style CPU address/data buses. A programmable interrupt output scheme allows device configuration for different interrupt signaling requirements.

National USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support datasheet

Datasheet

The USBN9603/4 are integrated USB Node controllers with enhanced DMA support. They are compatible with USB specification versions 1.0 and 1.1, and are advanced versions of the USBN9602. The devices integrate the required USB transceiver, a 3.3V regulator, a Serial Interface Engine (SIE), USB endpoint (EP) FIFOs, a versatile 8-bit parallel interface, a clock generator, and a MICROWIRE/PLUS™ interface. Seven endpoint pipes are supported, including one for the mandatory control endpoint and six for interrupt, bulk, and isochronous endpoints. Each endpoint pipe has a dedicated FIFO, with 8 bytes for the control endpoint and 64 bytes for the other endpoints. The 8-bit parallel interface supports multiplexed and non-multiplexed style CPU address/data buses. A programmable interrupt output scheme allows device configuration for different interrupt signaling requirements.