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National Semiconductor 5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops Datasheet
This document is a datasheet for the National Semiconductor 5476/DM5476/DM7476 series, which contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The device features separate preset and clear inputs to set or reset the outputs regardless of other input levels. Data is transferred to the outputs on the falling edge of the clock pulse, provided the J and K inputs remain constant while the clock is high.
The datasheet provides absolute maximum ratings, recommended operating conditions, and electrical characteristics for both the DM54 series (military/aerospace) and DM74 series (commercial) variants. It includes a function table, switching characteristics, and physical dimensions for various package types, including Dual-In-Line, Molded Dual-In-Line, Ceramic Flat, and Ceramic Dual-In-Line packages.
National Semiconductor DM7476 specifications
| Supply Voltage | 4.5V to 5.5V (DM5476), 4.75V to 5.25V (DM7476) |
|---|---|
| Clock Frequency | 15 MHz |
| Operating Temperature Range (DM54) | -55°C to +125°C |
| High Level Output Voltage | 2.4V to 3.4V |
| Low Level Output Voltage | 0.2V to 0.4V |
Source: National Semiconductor 5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops Datasheet
All National Semiconductor DM7476 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the data transfer timing for this flip-flop?
The data is transferred to the outputs on the falling edge of the clock pulse.
From: National Semiconductor 5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops Datasheet
Can the J and K inputs change while the clock is high?
No, the logic state of J and K inputs must not be allowed to change while the clock is high.
From: National Semiconductor 5476/DM5476/DM7476 Dual Master-Slave J-K Flip-Flops Datasheet
What is the function of the DM7476?
The device contains two independent positive pulse triggered J-K flip-flops with complementary outputs.
From: Fairchild DM7476 Dual Master-Slave J-K Flip-Flops Datasheet
How are data inputs transferred to the output?
Data is transferred to the outputs on the falling edge of the clock pulse.
From: Fairchild DM7476 Dual Master-Slave J-K Flip-Flops Datasheet