Key facts
- Model
- DS90CF561
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-07-04
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National Semiconductor DS90CF561/DS90CF562 LVDS FPD Link Datasheet
The DS90CF561/DS90CF562 chipset is designed to solve EMI and cable size problems associated with wide, high-speed TTL interfaces. The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDS data streams, while the DS90CF562 receiver converts these streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, the system transmits 18 bits of RGB data and 3 bits of LCD timing and control data at a rate of 280 Mbps per LVDS data channel.
Read onlineNational Semiconductor DS90CF561 specifications
| Data Bandwidth | Up to 105 Megabyte/sec |
|---|---|
| LVDS Swing | 290 mV |
| Package | 48-lead TSSOP |
| Clock Frequency | 20 to 40 MHz |
Source: National Semiconductor DS90CF561/DS90CF562 LVDS FPD Link Datasheet
All National Semiconductor DS90CF561 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the data transmission rate?
At a 40 MHz clock, the data throughput is 105 Megabytes per second.
From: National Semiconductor DS90CF561/DS90CF562 LVDS FPD Link Datasheet
Does the PLL require external components?
No, the PLL requires no external components.
From: National Semiconductor DS90CF561/DS90CF562 LVDS FPD Link Datasheet