Key facts
- Brand
- Cypress
- Model
- Ultra37000
- Category
- Other Electronics
- Documents
- 7
- Languages
- EN
- Last added
- 2012-06-05
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Cypress Ultra37000 Family Datasheet
The document describes the Cypress Ultra37000™ family of CMOS Complex Programmable Logic Devices (CPLDs), designed to provide high-density programmable logic solutions. The architecture is based on logic blocks connected by a Programmable Interconnect Matrix (PIM) and features an intelligent product term allocator.
Read onlineCypress Ultra37000 specifications
| Macrocells per device | 32 to 512 |
|---|---|
| I/O pins per device | 32 to 264 |
| Package pin count | 44 to 400 leads |
| Supply voltage options | 5 V and 3.3 V |
| Worst‑case combinatorial delay | 6.5 ns |
All Cypress Ultra37000 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What voltage supply is required for the Ultra37000 devices?
The Ultra37000 devices operate with a 5V supply.
How many macrocells are available in each logic block?
Each logic block features 16 macrocells.
What programming interfaces does the Ultra37000 family support?
The Ultra37000 family provides an IEEE 1149.1‑compliant JTAG interface for boundary scan and in‑system reprogramming (ISR).
What supply voltages can Ultra37000 CPLDs operate at?
Ultra37000 CPLDs are offered in 5 V and 3.3 V versions, both of which are 5 V‑tolerant.
What voltage versions are available for Ultra37000 CPLDs?
Both 5 V and 3.3 V versions are offered; the 5 V devices can support 5 V or 3.3 V I/O levels, while the 3.3 V devices operate at 3.3 V and are 5 V‑tolerant.
How many macrocells does the CY37128 device contain?
The CY37128 device includes 128 macrocells.