This document describes the features and characteristics of Cypress Semiconductor Corporation's Ultra37000 CPLD family, including In-System Reprogrammable (ISR) CMOS technology, high density, simple timing model, 3.3V and 5V versions, programmable bus-hold capabilities, and flexible clocking.
The Ultra37000 family from Cypress offers high‑density, ISR‑enabled CMOS CPLDs available in 5 V and 3.3 V versions. Devices range from 32 to 512 macrocells and 32 to 264 I/O pins, with five dedicated inputs and four synchronous clocks per device. The architecture includes a programmable interconnect matrix (PIM) and flexible clocking, providing a simple timing model with no fan‑out or routing delays.
The family supports JTAG‑based in‑system reprogramming, PCI‑compatible I/O, bus‑hold on all pins, and programmable slew‑rate control. Various package options are offered, from 44‑lead PLCC to fine‑pitch BGA, and development is supported by Cypress Warp tools and major third‑party EDA suites.
| Supply voltage | 5 V and 3.3 V versions |
|---|---|
| Macrocells | 32 to 512 |
| I/O pins | 32 to 264 |
| Dedicated inputs | 5 |
| Package options | 44‑400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, Fine‑Pitch BGA |
| Synchronous clocks | Four per device |
It uses a JTAG‑compliant serial interface for ISR programming.
Yes, the 5 V devices fully comply with the PCI Local Bus Specification.
Yes, bus‑hold capability is available on all I/O pins.