The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The family includes 5V and 3.3V versions, and supports PCI compatibility.
The Ultra37000 family offers high‑density, ISR‑reprogrammable CPLDs with 32 to 512 macrocells, 32 to 264 I/O pins, and four dedicated clock inputs. Both 5 V and 3.3 V versions are available, with programmable bus‑hold on all I/Os and flexible clock polarity control.
The guide includes selection tables for device speed bins, package options (44‑400 leads in PLCC, TQFP, BGA, etc.), architecture details such as the Programmable Interconnect Matrix, macrocell structure, product‑term allocator, timing model, JTAG/PCI compliance, and programming options using Cypress’s Warp tools or third‑party programmers.
| Macrocell count | 32 to 512 |
|---|---|
| I/O pins | 32 to 264 |
| Package leads | 44 to 400 |
| Supply voltage | 5 V and 3.3 V versions |
| Synchronous clocks per device | Four |
It supports an IEEE 1149.1‑compliant JTAG interface for both boundary‑scan and in‑system reprogramming (ISR).
Devices provide between 32 and 512 macrocells depending on the specific part.
Both 5 V and 3.3 V versions are available, with the 3.3 V devices being 5 V‑tolerant.