Cypress Ultra37000 family of high-performance CPLDs is a high-density programmable logic solution with 32 to 512 macrocells, 32 to 264 I/O pins and five dedicated inputs, including four clock pins.
The Ultra37000 family offers high‑density, ISR™ (In‑System Reprogrammable) CPLDs with 32 to 512 macrocells and 32 to 264 I/O pins. Devices are available in 5 V and 3.3 V versions, support four synchronous clocks, and provide programmable bus‑hold, slew‑rate control and low‑power modes. Packages range from 44‑lead PLCC to 400‑lead fine‑pitch BGA, all 5 V‑tolerant.
The architecture features a Programmable Interconnect Matrix (PIM) with no additional routing delay, 16‑macrocells per logic block, and a product‑term allocator that enables steering and sharing of up to 0‑16 product terms per macrocell. Programming is performed via an IEEE 1149.1‑compliant JTAG interface and Cypress ISR tools, with support for third‑party programmers and software such as Warp, Warp Professional and Warp Enterprise.
| Macrocells per device | 32 to 512 |
|---|---|
| I/O pins per device | 32 to 264 |
| Package pin count | 44 to 400 leads |
| Supply voltage options | 5 V and 3.3 V |
| Worst‑case combinatorial delay | 6.5 ns |
The Ultra37000 family provides an IEEE 1149.1‑compliant JTAG interface for boundary scan and in‑system reprogramming (ISR).
Ultra37000 CPLDs are offered in 5 V and 3.3 V versions, both of which are 5 V‑tolerant.
The worst‑case combinatorial propagation delay is 6.5 ns for all devices.