This document introduces the features and characteristics of the Cypress Ultra37000 CPLD family of products, including high density, simple timing model, 3.3V and 5V versions, PCI compatibility, programmable bus hold capabilities, intelligent product term allocator, flexible clocking, consistent packaging/pinout offering, etc.
The Ultra37000 family provides high‑density, ISR‑capable CPLDs with a simple timing model and JTAG‑based in‑system reprogramming. Devices are available in 5 V and 3.3 V versions, offering up to 512 macrocells and flexible I/O configurations.
The selection guide includes device tables, package options from 44 to 400 leads, clocking resources, bus‑hold and slew‑rate controls, and programming information for both Cypress‑provided and third‑party tools.
| Supply voltage options | 5 V and 3.3 V |
|---|---|
| Macrocell count | 32 to 512 |
| I/O pins | 5 to 264 |
| Package lead count | 44 to 400 leads |
| Clock resources | Four synchronous clocks per device |
| Bus‑hold capability | Programmable bus‑hold on all I/Os |
| Output slew rate | Fast or slow programmable |
| In‑system reprogramming interface | IEEE 1149.1‑compliant JTAG |
Both 5 V and 3.3 V versions are offered; the 5 V devices can support 5 V or 3.3 V I/O levels, while the 3.3 V devices operate at 3.3 V and are 5 V‑tolerant.
The CY37128 device includes 128 macrocells.
Up to 400 leads are available in various package types.
ISR uses a JTAG‑compliant serial interface.