The Ultra37000™ CPLD family provides a range of high-density programmable logic solutions, offering 32 to 512 macrocells and 32 to 264 I/O pins, with a simple timing model, 3.3V and 5V versions, PCI compatibility, and programmable bus-hold capabilities.
The document describes the Cypress Ultra37000™ family of CMOS Complex Programmable Logic Devices (CPLDs), designed to provide high-density programmable logic solutions. The architecture is based on logic blocks connected by a Programmable Interconnect Matrix (PIM) and features an intelligent product term allocator.
The Ultra37000 devices operate with a 5V supply.
Each logic block features 16 macrocells.
The Ultra37000 family supports up to 264 I/O pins.