Key facts
- Brand
- Cypress
- Model
- CY7C1327F
- Industry
- Industrial
- Documents
- 2
- Languages
- EN
- Last added
- 2012-05-04
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Cypress CY7C1327F 4-Mb (256K x 18) Pipelined Sync SRAM Datasheet
The CY7C1327F is a 4‑Mb (256K × 18) pipelined synchronous SRAM that operates from a +3.3 V core supply and supports both 3.3 V and 2.5 V I/O levels. It offers registered inputs and outputs for pipelined operation, fast clock‑to‑output times as low as 2.6 ns, and a selectable burst counter for Intel Pentium interleaved or linear burst sequences.
The device is offered in JEDEC‑standard 100‑pin TQFP and 119‑ball BGA packages. Detailed pin definitions, electrical characteristics, maximum ratings, and timing tables are provided to aid designers in integrating the SRAM into high‑performance systems.
Cypress CY7C1327F specifications
| Memory size | 4 Mb (256K × 18) |
|---|---|
| Core supply voltage | 3.3 V |
| I/O supply voltage | 3.3 V or 2.5 V |
| Package options | 100‑pin TQFP, 119‑ball BGA |
Source: Cypress CY7C1327F 4-Mb (256K x 18) Pipelined Sync SRAM Datasheet
All Cypress CY7C1327F documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What does the ZZ pin do?
The ZZ pin puts the SRAM into a power‑conservation sleep mode when asserted high.
From: Cypress CY7C1327F 4-Mb (256K x 18) Pipelined Sync SRAM Datasheet
What I/O voltage levels are supported?
Both 3.3 V and 2.5 V I/O supply voltages are supported.
From: Cypress CY7C1327F 4-Mb (256K x 18) Pipelined Sync SRAM Datasheet
What is the core supply voltage for the CY7C1327F?
The device operates from a +3.3 V core power supply.
Which pin enables a global write operation?
The GW pin (Global Write Enable) is active LOW and writes all bytes when asserted.