The document introduces the Ultra37000 series CMOS CPLDs products from Cypress Semiconductor Corporation. The products feature In-System Reprogrammable™ (ISR™) capability, allowing reconfiguration through JTAG interface. Additionally, the products offer high density, simple timing model, 3.3V and 5V versions, and programmable bus-hold capabilities.
The Ultra37000 family is a line of high‑performance, in‑system reprogrammable CMOS CPLDs offered by Cypress. It supports both 5 V and 3.3 V supply options, provides 32 to 512 macrocells, and offers 32 to 264 I/O pins in a variety of 44‑to‑400‑lead packages. The architecture features a Programmable Interconnect Matrix (PIM) and flexible macrocell designs, including buried and I/O macrocells with programmable bus‑hold and slew‑rate control.
The document details timing characteristics (6.5 ns worst‑case combinatorial delay, 4.5 ns registered delay), JTAG/PCI compliance, in‑system reprogramming (ISR) methods, and supported development tools such as Cypress Warp and third‑party EDA software. It also includes selection tables for device speed bins, package offerings, and macrocell counts.
| Supply Voltage | 5 V, 3.3 V |
|---|---|
| Macrocell Count | 32 to 512 |
| I/O Pin Count | 32 to 264 |
| Package Lead Count | 44 to 400 leads |
| Combinatorial Path Delay | 6.5 ns worst‑case |
| Registered Signal Delay | 4.5 ns worst‑case |
| JTAG Interface | IEEE 1149.1‑compliant |
The Ultra37000 devices operate with either a 5 V or a 3.3 V supply.
Devices in the Ultra37000 family provide between 32 and 512 macrocells.
The worst‑case combinatorial path delay is 6.5 ns.
Yes, it includes an IEEE 1149.1‑compliant JTAG interface for boundary‑scan and ISR.