Cypress Manuals

Key facts

Manuals

181

Models

71

Categories

1

Languages

EN

Last added

2026-09-28

Cypress models by category

Featured Cypress manuals

Cypress CY8C201A0 CapSense Express Slider Capacitive Controllers Data Sheet

Datasheet 38 pages · 1001 KB · EN

The CY8C201A0 is a CapSense Express slider controller from Cypress, offering configurable 5‑ or 10‑segment capacitive sliders, optional GPIO pins, and I2C‑based configuration with non‑volatile storage.

The data sheet provides pinout diagrams for QFN and SOIC packages, electrical specifications such as 2.4‑5.25 V supply, 1.5 mA active current, 4 µA deep‑sleep current, and details on operating modes, sleep control, and I2C communication.

Covers: Pinouts · Typical Circuits · I2C Interface · Operating Modes · Electrical Specifications · Package Information

Latest Cypress manuals

• Cypress CY8C201A0 CapSense Express Slider Capacitive Controllers Data Sheet

  Datasheet 38 pages · 1001 KB · EN

  The Cypress CY8C201A0 CapSense Express Slider Capacitive Controllers data sheet details features, pinouts, electrical specs, and I2C interface.

• CYPRESS CY8C24123A CY8C24223A CY8C24423A PSoC

  This datasheet introduces the features and characteristics of the CY8C24123A, CY8C24223A, and CY8C24423A PSoC devices.

• CYPRESS CY8C21123 CY8C21223 CY8C21323 PSoC

  Features 1.71V to 5.5V Operating Range Low Power CapSense Block Configurable Capacitive Sensing Elements Supports Combination of CapSense Buttons, Sliders, Touchpads, Touch Screens, and Proximity Sensor Powerful Harvard Architecture Processor M8C Processor Speeds Running to 24 MHz Low Power at High Speed Interrupt Controller Temperature Range: -40

• CYPRESS CY7C1354BV25 CY7C1356BV25 Data Sheet

  This document describes the features and characteristics of the 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture CY7C1354BV25 and CY7C1356BV25, produced by Cypress Semiconductor Corporation.

• CYPRESS W228B Manual

  PRELIMINARY FTG for Integrated Core Logic with 133-MHz FSB W228B is a product of Cypress Semiconductor Corporation. It uses Cypress's Spread Spectrum technology to maximize EMI suppression. It provides two CPU clocks with frequencies of 66/100/133 MHz. It provides 12 100 MHz SDRAM clocks. It provides a PCI clock. It provides an APIC clock with a frequency of 33 MHz, which is synchronized to the CPU clock. It provides two 48-MHz clocks (non-Spread Spectrum), optimized for USB reference input and video dot clock. It provides three 3V 66-MHz fixed clocks. It provides a 14.31818-MHz reference clock. It provides power down control. It provides an I2C™ interface for turning off unused clocks.

• CYPRESS CY8C27143 CY8C27243 CY8C27443 CY8C27543 CY8C27643 Data Sheet

  This data sheet provides detailed information on the PSoC™ Mixed Signal Array

• CYPRESS CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18 72-Mbit QDR -II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) handbook

• CYPRESS CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 36-Mbit QDR -II SRAM 2-Word Burst Architecture handbook

• CYPRESS CY7C1381D CY7C1381F CY7C1383D CY7C1383F 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM handbook

  This datasheet provides information on the features of 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F, including support for 133 MHz bus operations, 512K × 36 and 1M × 18 common IO, 3.3V core power supply (VDD), 2.5V or 3.3V IO supply (VDDQ), Fast clock-to-output time — 6.5 ns (133 MHz version), Provides high performance 2-1-1-1 access rate, etc.

• CYPRESS CY7C1370DV25 CY7C1372DV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL Architecture handbook

  18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture CY7C1370DV25 CY7C1372DV25 is a high-performance SRAM produced by CYPRESS. It has the characteristics of full synchronization, pipeline, burst operation, and zero wait state.

• CYPRESS CY7B993V CY7B994V High-speed Multi-phase PLL Clock Buffer handbook

  This data sheet provides a detailed overview of the Cypress CY7B993V and CY7B994V high-performance multi-phase PLL clock buffers.

• CYPRESS CY7B923 CY7B933 HOTLink Transmitter/Receiver handbook

  The CY7B923 HOTLink™ Transmitter and CY7B933 HOTLink Receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and twisted pair).

• CYPRESS CY7C1379B DATA SHEET

  The document mainly introduces the characteristics of CY7C1379B, including supporting up to 133MHz bus operations, zero wait states, compatibility with ZBT™ devices, internally self-timed output buffer control, registered inputs, byte write capability, 256K x 32 common I/O architecture, single 3.3V power supply, fast clock-to-output time, clock enable (CEN) pin, synchronous self-timed write, asynchronous output enable, JEDEC standard 100 TQFP and 165 fBGA packages, burst capability, linear or interleaved burst order, and low standby power.

• CYPRESS CY62127DV30 DATA SHEET

• CYPRESS CY7C1338G DATA SHEET

  The CY7C1338G is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic.

Which document do I need?

Questions answered in Cypress manuals

Cypress manuals by category