The document describes the Ultra37000™ family of CMOS CPLDs from Cypress Semiconductor Corporation, which provides a range of high-density programmable logic solutions. The product features In-System Reprogrammable™ (ISR™) capability with JTAG interface for reconfigurability, design changes do not cause pinout or timing changes. The features include high density, simple timing model, 3.3V and 5V versions, PCI compatibility, programmable bus-hold capabilities, flexible clocking, consistent package and pinout offering, etc.
The Ultra37000 CPLD Family handbook describes Cypress's high‑density, in‑system reprogrammable (ISR) CPLDs. It covers the architecture, including the Programmable Interconnect Matrix (PIM), logic blocks, macrocell options, and low‑power versus high‑speed modes. Detailed tables list device options, macrocell counts, I/O pin counts, package types, and speed bins for both 5 V and 3.3 V versions.
The document also explains timing characteristics, JTAG/PCI compliance, in‑system reprogramming methods, and software support such as the Warp design suite. Programming options, third‑party tool compatibility, and bus‑hold features are included to aid designers in implementing Ultra37000 devices in their systems.
| Macrocells per device | 32 to 512 |
|---|---|
| I/O pins per device | 32 to 264 |
| Dedicated clock inputs | Four synchronous clocks per device |
Each Ultra37000 device provides between 32 and 512 macrocells.
The Ultra37000 family uses an IEEE 1149.1‑compliant JTAG interface for in‑system reprogramming and boundary scan.
Yes, the 5 V Ultra37000 devices fully comply with the PCI Local Bus Specification.