Find DS90CF562MTD suppliers
The DS90CF561/DS90CF562 chipset is designed to solve EMI and cable size problems associated with wide, high-speed TTL interfaces. The DS90CF561 transmitter converts 21 bits of CMOS/TTL data into three LVDS data streams, while the DS90CF562 receiver converts these streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, the system transmits 18 bits of RGB data and 3 bits of LCD timing and control data at a rate of 280 Mbps per LVDS data channel.
| Data Bandwidth | Up to 105 Megabyte/sec |
|---|---|
| LVDS Swing | 290 mV |
| Package | 48-lead TSSOP |
| Clock Frequency | 20 to 40 MHz |
At a 40 MHz clock, the data throughput is 105 Megabytes per second.
No, the PLL requires no external components.
Yes, it is compatible with the TIA/EIA-644 LVDS standard.