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Atmel ATF1502ASV High-Density CPLD Datasheet
Datasheet 22 pages · 205 KB · EN
The document describes the Atmel ATF1502ASV as a high-density, high-performance CPLD utilizing electrically-erasable technology. It features 32 macrocells and operates within a 3.0 to 3.6V range.
Key capabilities include in-system programmability (ISP) via JTAG, support for IEEE Std. 1149.1 boundary-scan testing, and advanced power management options such as pin-controlled standby mode and programmable pin-keeper inputs.
Atmel ATF1502AS specifications
| Operating Voltage Range | 3.0 to 3.6V |
|---|---|
| Number of Macrocells | 32 |
| Maximum Pin-to-pin Delay | 15 ns |
| Registered Operation Frequency | up to 77 MHz |
| Number of Pins (PLCC/TOFP) | 44 |
| Program/Erase Cycles | 10,000 |
| Data Retention Time | 20 years |
All Atmel ATF1502AS documents by type
Datasheet 2
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the operating voltage range for this device?
The device operates within a voltage range of 3.0 to 3.6V.
Does the ATF1502ASV support in-system programming?
Yes, it supports In-System Programmability (ISP) via JTAG.
What is the maximum pin-to-pin delay for this device?
The maximum pin-to-pin delay is 7.5 ns.
How many program/erase cycles can the EEPROM support?
The device supports up to 100 program/erase cycles.