Atmel ATF1502AS CPLD Preliminary Datasheet

High density, high performance electrically erasable complex programmable logic device, 32 macrocells, 5 product terms per macrocell, expandable up to 40 per macrocell, 44 pins, 7.5 ns maximum pin-to-pin delay, registered operation up to 125 MHz, enhanced routing resources


Atmel ATF1502AS CPLD Preliminary Datasheet - cover page
Brand
Atmel
Category
Chips
Document type
Datasheet
Language
English
Pages
18
File format
PDF
File size
349 KB
Published
07 June, 2012
Updated
30 September, 2023
MD5 checksum
9E5E6E94DE56035D25F50FBAAB5B3DC7

About this manual

The document describes the ATF1502AS as a high performance, high density Complex Programmable Logic Device (CPLD) utilizing Atmel's proven electrically erasable technology. It features 32 macrocells and up to 36 inputs, integrating logic from various TTL, SSI, MSI, LSI, and classic PLDs.

What's inside

  • Features
  • Description
  • Block Diagram
  • Macrocell Structure
  • In-System Programmability
  • Speed/Power Management

Frequently asked questions

What is the maximum pin-to-pin delay for this device?

The maximum pin-to-pin delay is 7.5 ns.

How many program/erase cycles can the EEPROM support?

The device supports up to 100 program/erase cycles.

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