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Cypress Semiconductor CY7C1354BV25/CY7C1356BV25 Pipelined SRAM Datasheet
The CY7C1354BV25 and CY7C1356BV25 are synchronous pipelined burst SRAMs designed to support unlimited true back-to-back Read/Write operations with no wait states. They feature advanced (NoBL) logic that allows data to be transferred on every clock cycle, dramatically improving system throughput for applications requiring frequent Write/Read transitions.
These devices operate at a single 2.5V power supply and are available in speed grades of 225, 200, and 166 MHz. They support burst capabilities in both linear and interleaved orders and include features such as byte write capability, synchronous self-timed writes, and IEEE 1149.1 JTAG Boundary Scan.
Cypress CY7C135 specifications
| Organization | 4K x 8 |
|---|---|
| Technology | 0.65-micron CMOS |
| Maximum Access Time (15ns variant) | 15 ns |
| Package Type | 52-pin PLCC |
Source: Cypress Semiconductor CY7C135/CY7C1342 Dual-Port Static RAM Datasheet
All Cypress CY7C135 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the architecture of these SRAMs?
They utilize NoBL (No Bus Latency) logic to support unlimited true back-to-back Read/Write operations with no wait states.
From: Cypress Semiconductor CY7C1354BV25/CY7C1356BV25 Pipelined SRAM Datasheet
Are these devices pin-compatible?
Yes, they are pin compatible and functionally equivalent to ZBT devices.
From: Cypress Semiconductor CY7C1354BV25/CY7C1356BV25 Pipelined SRAM Datasheet
What is the difference between CY7C135 and CY7C1342?
The CY7C1342 includes semaphores that provide a means to allocate portions of the dual-port RAM or any shared resource, while the CY7C135 does not.
From: Cypress Semiconductor CY7C135/CY7C1342 Dual-Port Static RAM Datasheet
Can both ports access the same memory location simultaneously?
Yes, true dual-ported memory cells allow simultaneous reads of the same memory location.
From: Cypress Semiconductor CY7C135/CY7C1342 Dual-Port Static RAM Datasheet
How many chip enable pins are provided?
The device includes three synchronous chip‑enable pins: CE1, CE2, and CE3.
From: Cypress CY7C1354B & CY7C1356B Pipelined SRAM Datasheet