CYPRESS CY7C1354B CY7C1356B Manual

Update: 29 September, 2023

The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature is very impressive.

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File format: PDF

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MD5 Checksum: 870E06533AB45BB5C89EF42FA26D0F4E

Publication date: 04 June, 2012

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PDF Link: CYPRESS CY7C1354B CY7C1356B Manual PDF