This document describes the features and characteristics of the 256K x 36/512K x 18 Pipelined SRAM with NoBL™ Architecture CY7C1354BV25 and CY7C1356BV25, produced by Cypress Semiconductor Corporation.
The CY7C1354BV25 and CY7C1356BV25 are synchronous pipelined burst SRAMs designed to support unlimited true back-to-back Read/Write operations with no wait states. They feature advanced (NoBL) logic that allows data to be transferred on every clock cycle, dramatically improving system throughput for applications requiring frequent Write/Read transitions.
These devices operate at a single 2.5V power supply and are available in speed grades of 225, 200, and 166 MHz. They support burst capabilities in both linear and interleaved orders and include features such as byte write capability, synchronous self-timed writes, and IEEE 1149.1 JTAG Boundary Scan.
| Operating Voltage | 2.5V |
|---|---|
| Maximum Access Time (225 MHz) | 2.8 ns |
They utilize NoBL (No Bus Latency) logic to support unlimited true back-to-back Read/Write operations with no wait states.
Yes, they are pin compatible and functionally equivalent to ZBT devices.