Key facts
- Brand
- Atmel
- Model
- ATV2500B
- Industry
- Industrial
- Documents
- 3
- Languages
- EN
- Last added
- 2012-03-27
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Atmel ATV2500 and ATV2500B Application Note
The document introduces the ATV2500 and ATV2500B programmable logic devices, describing their 40/44‑pin packages, 24 macrocells, and the macrocell architecture with sum terms, registers, and product terms. It shows how each I/O pin provides programmable polarity control and an individual output‑enable term.
Detailed sections cover macrocell configurations, asynchronous reset, synchronous preset groups, clock options, and the ability of the ATV2500B to use D‑type or T‑type registers. A sample CUPL simulation input file and example code snippets for both ABEL and CUPL are provided.
Atmel ATV2500B specifications
| Package | 40/44‑pin |
|---|---|
| Macrocells | 24 |
| Sum terms per macrocell | 3 |
| Registers per macrocell | 2 |
| Product terms per macrocell | 17 |
| I/O pin polarity control | Programmable |
| Output enable per I/O pin | Individual product term |
| Clock options (ATV2500B) | Three different options |
| Buried combinatorial nodes (ATV2500B) | Supported |
All Atmel ATV2500B documents by type
How to use the product for one specific task, with worked examples.
Questions answered in these manuals
What package types are available for the ATV2500?
The ATV2500 and ATV2500B are available in a 40/44‑pin package.
How many macrocells does each device have?
Each device contains 24 macrocells.
What are the AC timing parameters used for Atmel PLDs?
Atmel PLDs use parameters such as tpp, tpps, tppg, top, tepe, and others to describe pin‑to‑pin, feedback, and combinatorial delays.
From: Atmel PLD Architectures Simplify Timing Calculation Application Note
Can the timing of Atmel PLDs be predicted without simulation tools?
Yes, because the devices have deterministic, path‑independent delays, the AC timing parameters allow hand calculation of delays in a few minutes.
From: Atmel PLD Architectures Simplify Timing Calculation Application Note