Industrial

cdc5801 is a low jitter clock multiplier and divider with programmable delay and phase alignment, supporting x4, x6, x8 multiplication, supporting input frequency from 19mhz to 125mhz, output frequency from 150mhz to 500mhz.

The CDC5806 is a clock generator for digital TV applications. It synthesizes video clocks, audio clocks, CPU clock, ASIC clock, USB clock, and memory card clock from a 54-MHz system clock. It utilizes three phase-locked loops (PLLs) to generate different frequencies, and it features high performance, low jitter, and low peak-to-peak clock jitter.

The CDC582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input signals. It is specifically designed to operate at speeds from 50 MHz to 100 MHz or lower.

The CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN).

Alpha Industries, Inc.'s silicon Schottky diode chips are intended for use as detector and mixer devices in hybrid integrated circuits at frequencies from below 100 MHz to higher than 40 GHz. The chips feature low capacitance, ZBD and low barrier designs, P-type and N-type junctions, and large bond pads.

The CDC509 is a high-performance, low-jitter, low-skew phase-lock loop (PLL) clock driver from Cypress Semiconductor. It uses a PLL to precisely align the feedback (FBOUT) output to the clock (CLK) input signal, both in frequency and phase. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3.3 V VCC and is designed to drive up to five clock loads per output. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC509 does not require external RC networks. The PLL's loop filter is integrated on-chip, reducing PCB area.

The CDC392 is a 1-to-6 line clock driver with selectable polarity and 3-state outputs. It is designed for clock distribution and clock generation applications, providing low output skew. The inputs are TTL-compatible and the outputs are CMOS-compatible. Various combinations of true and complementary outputs can be obtained using the polarity control inputs. The distributed VCC and GND pins help reduce switching noise. The outputs have high drive capability (-32mA IOH, 32mA IOL). The CDC392 is built using state-of-the-art EPIC-ΙΙB BiCMOS design, which significantly reduces power dissipation. It is packaged in a plastic small-outline package.

The CDC351 is a high-performance clock driver circuit from Texas Instruments that distributes one input clock signal to 10 output clock signals with minimum skew. The CDC351 operates at 3.3 V VCC, and has high drive current and low power consumption.

The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input. The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. The CDC341 is characterized for operation from 0°C to 70°C.

The CDC340 is a high-performance clock driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a high state regardless of the A input. The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. The CDC340 is characterized for operation from 0°C to 70°C.

The CDC339 is a high-performance, low-skew clock driver specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. It features low output skew and low pulse skew, TTL-compatible inputs and outputs, distributes one clock input to eight outputs (four same-frequency outputs and four half-frequency outputs), distributed VCC and ground pins to reduce switching noise, high-drive outputs, state-of-the-art EPIC-IIIB BiCMOS design to reduce power dissipation, and multiple package options.

cdc337 is a single clock input, eight-way clock output clock driver with low output skew and low pulse skew launched by texas instruments, which can simultaneously output clock frequency and one-half of the clock frequency.

The CDC330 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring output signals at both the primary clock frequency and one-half the primary clock frequency. This device contains two banks that fan out one input to three same-frequency outputs and one bank that fans out one input to four half-frequency outputs with minimum skew for clock distribution. Each bank of Y outputs switch in phase and at the same frequency as its clock (A) input. The four Q outputs switch at one-half the frequency of their clock (2A) input. When the output-enable (2OE) input is low and the preset (PRE) input is high, the Q outputs toggle on high-to-low transitions of 2A. Taking PRE low asynchronously presets the Q outputs to...