Industrial

The CDC2582 is a high-performance, low-skew, low-jitter clock driver that uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input.

The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input signals.

The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2510 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing

the cdc2509c is a 3.3v phase-lock loop clock driver from ti. the device supports frequencies from 25mhz to 125mhz and offers low distortion and jitter.

cdc203 is a 3.3v six-way switching circuit produced by texas instruments. It is suitable for applications requiring low skew between switching outputs. cdc203 adopts flow-through architecture, optimizes pcb layout, center-pin vcc and gnd pin configuration can minimize high-speed switching noise. The device is manufactured using 1-μm epic (enhanced performance implanted cmos) process, has a typical latch-up immunity of 500ma at 125℃, and is packaged in plastic small-outline package.

The CDC204 is a device that contains six independent inverters, designed for applications requiring low skew between switching outputs. It has CMOS-compatible inputs and outputs, with a flow-through architecture that optimizes PCB layout. The device is manufactured using the EPIC (Enhanced-Performance Implanted CMOS) 1-µm process, and has a high latch-up immunity. It is available in various package options.

The CDC208 is a dual 1-line to 4-line clock driver designed for clock distribution applications. It features low-skew propagation delay, TTL-compatible inputs, CMOS-compatible outputs, flow-through architecture for optimized PCB layout, center-pin VCC and GND pin configurations to minimize high-speed switching noise, and is manufactured using the EPIC (Enhanced-Performance Implanted CMOS) 1-µm process. The device also offers output-enable inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the input signal.

CDC208 is a clock driver produced by TI company, it can distribute one input signal to four output terminals with minimum jitter and high reliability.

cdc2351 is a clock driver circuit from dallas semiconductor that distributes one input (a) to ten outputs (y) with minimum skew for clock distribution. the output-enable (oe) input disables the outputs to a high-impedance state. each output has an internal series damping resistor to improve signal integrity at the load. the cdc2351 operates at nominal 3.3-v vcc.

The CDC2509 is a 3.3V phase-lock loop clock driver that uses a PLL to precisely align the feedback output to the clock input signal in both frequency and phase. This product is specifically designed for use with synchronous DRAM. The CDC2509 operates at 3.3V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control inputs (1G and 2G). When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2509 does not require an external RC network.

The CDC2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509A operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products...

cdc2509b 3.3-v phase-lock loop clock driver is a phase-lock loop clock distributor for synchronous dram applications. it distributes one clock input to one bank of five and one bank of four outputs. each output bank has a separate output enable. the external feedback (fbin) terminal is used to synchronize the outputs to the clock input. cdc2509b operates at 3.3-v vcc. it also provides integrated series damping resistors, making it ideal for driving point-to-point loads.

The document describes the features and characteristics of the CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER, including low-output skew, differential low-voltage pseudo-ECL (LVPECL)-compatible inputs and outputs, output reference voltage, and single-ended LVPECL-compatible output enable.

This is a 5.0V precision micropower voltage regulator with 150mA output current capability. The output voltage accuracy is ±2.0% with a maximum dropout voltage of 0.6V at 150mA. It can output 150mA current and is especially suitable for any battery-powered microprocessor equipment. Microprocessor control logic includes an active RESET (with DELAY) and a FLAG monitor that can be used to provide an early warning signal to the microprocessor of a potential impending RESET signal. The use of the FLAG monitor allows the microprocessor to finish any signal processing before the RESET shuts the microprocessor down. The active RESET circuit operates correctly at an output voltage as low as 1.0V. The RESET function is activated during the power up sequence or during normal operation if the output voltage drops outside the regulation limits. The reset threshold voltage can be decreased by the connection of an external resistor divider to RADJ lead. The regulator is protected against reverse battery, short circuit, and thermal overload conditions. The device can withstand load dump transients making it suitable for use in automotive environments. The device has also been optimized for EMC conditions.