Industrial

The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit wi

CDCV857 is a 2.5V phase-locked loop (PLL) clock driver from TI, which is used for double data rate synchronous DRAM applications. The device adopts low-power design, and has low jitter, low skew, zero delay and other characteristics. Its working frequency range is 60MHz to 200MHz, and it can drive 10 differential clock outputs. When the input clock frequency is lower than 20MHz, the device will enter low power mode, and shut down the PLL.

The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low-frequency condition and after applying a >20-MHz input signal this detection circuit turns on the PLL again.

The document describes a phase-locked loop clock driver for double data-rate synchronous DRAM applications. It features spread spectrum clock compatibility, operating frequency range of 60 to 140 MHz, low jitter, and the capability to distribute one differential clock input to ten differential outputs. It also includes a two-line serial interface, high-impedance state, and low quiescent current consumption.

CDCV304 is a PCI-X clock buffer produced by Texas Instruments. It operates at a frequency of 0MHz to 140MHz. The low output skew is less than 100ps. It can distribute one clock input to one bank of four output clocks. When OE is low, the output is low. CDCV304 operates at a voltage of 3.3V. It is suitable for automotive and industrial applications and has a working temperature range of -40°C to 85°C.

SCAS688A is a 1.8V phase-locked loop clock driver for double data rate (DDR II) applications. It is spread spectrum clock compatible and operates at a frequency range of 10 MHz to 400 MHz. It has features such as low current consumption, low jitter, low output skew, and low phase offset. It distributes one differential clock input to ten differential outputs.

The CDCR61A is an independent crystal clock generator from Texas Instruments. It supports 400MHz differential clock signal output, and provides single-ended 1/2 clock signal output. It can be selected to output 300MHz or 400MHz clock signal.

This file is the scas727b manual for the cdcp1803 clock driver

The product is a clock buffer that supports 1:3 LVPECL clock output and programmable divider. It features low output skew, wide common mode range, differential input stage and single-ended input signal VBB bias voltage output.

The CDCM1802 is a clock buffer with a programmable divider, LVPECL I/O and additional LVCMOS output. It distributes one differential clock input to one LVPECL differential clock output and one LVCMOS single-ended output. The programmable output divider is suitable for LVPECL and LVCMOS outputs. The 1.6-ns output skew between LVCMOS and LVPECL transitions minimizes noise. The device operates at a supply voltage of 3.3 V (2.5 V functional) and has a signaling rate of up to 800 MHz LVPECL and 200 MHz LVCMOS. The differential input stage has a wide common-mode range and also provides a VBB bias voltage output for single-ended input signals. The receiver input threshold is ±75 mV. The device is packaged in a 16-pin QFN package (3 mm x 3 mm).

The CDCLVP110 is a low-voltage 1:10 LVPECL/HSTL with selectable input clock driver. It distributes one differential clock input pair (CLK0, CLK1) to ten pairs of differential LVPECL clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources to an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines. If single-ended input operation is required, the VBB reference voltage output is used. In this case, the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

The CDCLVD110 is a programmable low-voltage 1:10 LVDS clock driver. It features low-output skew, distribution of one pair of differential clock inputs to 10 pairs of differential clock outputs, VCC range of 2.5V, and a typical signaling rate capability of up to 1.1 GHz.

CDCFR83 is a Direct Rambus clock generator from Texas Instruments that provides a 533 MHz clock source for Direct Rambus memory systems for an 1066 MHz data transfer rate. CDCFR83 can also synchronize the Rambus channel clock domain with an external system clock or processor clock. CDCFR83 employs three power operating modes to minimize power consumption for mobile applications and other power-sensitive applications. CDCFR83 is powered by a single 3.3 V supply and consumes 120 mW (typical) and is packaged in a Shrink Small-Outline Package (DBQ). CDCFR83 supports frequency multipliers of 4, 6, 8, 16/3, does not require external components for PLL, supports independent channel clocking, and has spread spectrum clocking tracking capability to reduce EMI. CDCFR83 is designed for use with TI's 133 MHz clock synthesizers CDC924 and CDC921. Its cycle-to-cycle jitter is less than 40 ps at 533 MHz. CDCFR83 has been certified by Gigatest Labs to exceed the Rambus DRCG validation requirement and supports an industrial temperature range of -40°C to 85°C.

the cdcf5801 is a low-jitter clock multiplier that can multiply the input clock frequency by 1, 2, 4, or 8 times. The output frequency range is 25 mhz to 280 mhz, and the input frequency range is 12.5 mhz to 240 mhz. It has single-ended input and differential output, and can drive lvpecl, lvds, and lvttl.