Industrial

The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control.

The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to support Pentium/82430X/82430VX and PentiumPro 82440FX chipsets. It provides four host-clock outputs (HCLKn) that are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided. All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the X1 input instead of the crystal input.

cdc9841 pc motherboard clock synthesizer/driver with 3-state outputs

The CDC960 is a clock synthesizer/driver and buffer that generates CPU, PCI, PCI/LDT, USB, FDC, and REF system clock signals to support PCs with an AMD-K8 Clawhammer-class system. All output frequencies are generated from a 14.318-MHz crystal input.

This document is about CDC950 clock synthesizer/driver, which can generate 8 host clock (100/133 MHz) clocks, 1 CLK33 clock (3.3V, 33.3MHz), 1 REFCLK clock (3.3V, 14.318MHz) and 2 3V48 clocks (3.3V, 180° shifted pairs, 48MHz)

cdc930 133-mhz differential clock synthesizer/driver for pc motherboards with 3-state outputs

The CDC924 is a clock synthesizer/driver for PC motherboards that supports Pentium III class motherboards. It uses a 14.318 MHz crystal input to generate multiple output frequencies. The CDC924 includes spread spectrum clocking (SSC) with 0.5% downspread for reduced electromagnetic interference (EMI) performance. It also features power management control terminals, low output skew and jitter for clock distribution, and supports 2.5 V and 3.3 V supplies. The CDC924 generates various clocks including CPU, PCI, APIC, and REF clock signals.

cdc922 133-mhz clock synthesizer/driver for pc motherboards with 3-state outputs

This document describes the features and characteristics of CDCR81 DIRECT RAMBUS CLOCK GENERATOR SCAS606B, including support for Direct Rambus memory subsystem, synchronization with external system or processor clock, three power operating modes, single 3.3V supply, wide frequency range for phase-locked loop input, etc.

CDC857-2 and CDC857-3 are 2.5-/3.3-V phase-lock loop clock drivers for Double Data Rate Synchronous DRAM applications. It distributes one differential clock input to ten differential outputs. External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input. It operates at VCC = 2.5 V and AVCC = 3.3 V. And it is packaged in plastic 48-pin (DGG) thin shrink small-outline package (TSSOP).

the cdc516 is a phase-lock loop clock driver from texas instruments that is specifically designed for use with synchronous drams. it uses a phase-lock loop (pll) to precisely align, in both frequency and phase, the feedback output (fbout) to the clock (clk) input signal. the device operates at 3.3v vcc and is designed to drive up to five clock loads per output. four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. each bank of outputs can be enabled or disabled separately via the 1g, 2g, 3g, and 4g control inputs. when the g inputs are high, the outputs switch in phase and frequency with clk; when the g inputs are low, the outputs are disabled to the logic-low state. unlike many products containing plls, the cdc516 does not require external rc networks. the loop filter for the pll is included on-chip, minimizing the number of external components required and improving product reliability.

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-Ω transmission line. The feedback input (FBIN) is used to synchronize the output clocks.