The CDC339 is a high-performance, low-skew clock driver specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. It features low output skew and low pulse skew, TTL-compatible inputs and outputs, distributes one clock input to eight outputs (four same-frequency outputs and four half-frequency outputs), distributed VCC and ground pins to reduce switching noise, high-drive outputs, state-of-the-art EPIC-IIIB BiCMOS design to reduce power dissipation, and multiple package options.