Industrial

CDC303 is an eight-bit divide-by-two circuit/clock driver from TI. The device has low output skew and pulse skew, with a maximum output skew of 1ns and a maximum pulse skew of 1ns. CDC303's inputs and outputs are TTL-compatible. The device is available in plastic small-outline (D) package and standard plastic (N) 300mil DIP packages.

The CDC304 is a circuit with 8 flip-flops designed to have low skew between outputs. It has a maximum output skew of 1ns and maximum pulse skew of 1.5ns. The product features TTL-compatible inputs and outputs, and utilizes center-pin VCC and GND configurations to minimize high-speed switching noise. It is suitable for clock drivers where a divide-by-two function is required.

CDC305 is a clock driver produced by TI company. This clock driver has TTL-compatible inputs and outputs, low skew between outputs, and eight outputs, four of which are synchronized with the CLK signal and four of which are out of phase with the CLK signal.

The CDC318 is a high-performance clock buffer that distributes one input (A) to 18 outputs (Y) with minimum skew for clock distribution. The CDC318 operates from a 3.3-V power supply, and is characterized for operation from 0°C to 70°C. The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs (SDATA and SCLOCK) provide integrated pullup resistors (typically 140 kΩ) and are 5-V tolerant. Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register.

cdc318a is a clock buffer produced by texas instruments. it supports 100mhz clock frequency and can output 18 clock signals at the same time.

CDC319 is a 1-to-10 clock buffer that supports SDRAM clock buffering applications. The output skew (tsk(o)) is less than 250 ps, and the pulse skew (tsk(p)) is less than 500 ps. It supports up to two unbuffered SDRAM DIMMs (Dual Inline Memory Modules). The I2C serial interface provides individual enable control for each output. It operates at 3.3V. Distributed VCC and ground pins reduce switching noise. The ESD protection voltage exceeds 2000V, meeting the requirements of MIL-STD-883 Method 3015. It is packaged in a 28-pin Shrink Small Outline (DB) package.

cdc328 is a clock driver produced by Texas Instruments. It can distribute one input signal to six output ports, with low output skew and optional positive and negative polarity. It is mainly used for clock distribution and clock generation applications.

CDC328A 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY is a clock driver that provides 1 input and 6 outputs, with polarity control.

CDC329 is a clock driver product from Texas Instruments. It can distribute one input clock signal to six output ports and provide low switching noise, high drive output and other features.

CDC2510C is a 3.3V low-skew, low-jitter, phase-lock loop (PLL) clock driver released by TI. It uses a PLL to precisely align the feedback output (FBOUT) with the clock input (CLK) signal in both frequency and phase. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V. It also provides integrated series damping resistors, making it ideal for driving point-to-point loads. One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled through a single output enable input. When the G input is high, all outputs are enabled.

The CDC2516 3.3-V Phase-Lock Loop Clock Driver is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2516 operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. Four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. Each bank of outputs can be enabled or disabled separately via the 1G, 2G, 3G, and 4G control inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2516 does not require external RC network.

The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536 operates at 3.3-V VCC and is designed to drive a 50-Ω transmission line. The CDC2536 also provides on-chip series-damping resistors, eliminating the need for external RC network.