The CDC392 is a 1-to-6 line clock driver with selectable polarity and 3-state outputs. It is designed for clock distribution and clock generation applications, providing low output skew. The inputs are TTL-compatible and the outputs are CMOS-compatible. Various combinations of true and complementary outputs can be obtained using the polarity control inputs. The distributed VCC and GND pins help reduce switching noise. The outputs have high drive capability (-32mA IOH, 32mA IOL). The CDC392 is built using state-of-the-art EPIC-ΙΙB BiCMOS design, which significantly reduces power dissipation. It is packaged in a plastic small-outline package.
The CDC392 is a clock-driver circuit that distributes a single input signal to six outputs with minimum skew, suitable for clock-distribution and clock-generation applications. It features TTL-compatible inputs and CMOS-compatible outputs, allowing various combinations of true and complementary outputs through polarity-control inputs. An output-enable input disables the outputs to a high-impedance state.
| Operating Temperature Range | -40°C to 85°C |
|---|---|
| Supply Voltage | 4.75 V to 5.25 V |
| High-Level Output Current | -32 mA |
| Low-Level Output Current | 32 mA |
| Input Clock Frequency | 90 MHz |
| Package Type | Small-Outline Package |
The CDC392 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew.
Yes, the polarity-control inputs allow various combinations of true and complementary outputs to be obtained.
The output-enable (OE) input is provided to disable the outputs to a high-impedance state.