cdc5801 is a low jitter clock multiplier and divider with programmable delay and phase alignment, supporting x4, x6, x8 multiplication, supporting input frequency from 19mhz to 125mhz, output frequency from 150mhz to 500mhz.
The CDC5801 is a low jitter clock multiplier and divider device that accepts a single-ended reference clock (REFCLK) and provides a differential output pair (CLKOUT/CLKOUTB). It supports multiplication ratios of x4, x6, and x8, as well as division ratios of /2, /3, and /4, with output frequencies ranging from 12.5 MHz to 500 MHz. The device operates with a reference input frequency between 19 MHz and 125 MHz.
| Output Frequency Range | 12.5 MHz to 500 MHz |
|---|---|
| Input Frequency Range | 19 MHz to 125 MHz |
| Multiplication Ratios | x4, x6, x8 |
| Division Ratios | /2, /3, /4 |
| Typical Phase Jitter | 8.0-ps |
| Package Type | DBQ |
The device supports multiplication ratios of x4, x6, and x8.
The device supports division ratios of /2, /3, and /4.
No, the device requires no external components for the PLL.
The output clocks can be delayed or advanced in steps of 2.6 mUI.