The CDC586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN).
The CDC586 is a high-performance, low-skew, low-jitter clock driver that uses a phase-lock loop (PLL) to align clock output signals in frequency and phase to the clock input (CLKIN). It operates at 3.3 V and is designed to drive properly terminated 50-Ω transmission lines, making it suitable for synchronous DRAM and high-speed microprocessor applications.
| Operating Temperature Range | 0°C to 70°C |
|---|---|
| Input Frequency Range (Config A) | 50 MHz to 100 MHz |
| Input Frequency Range (Config B) | 25 MHz to 50 MHz |
| Output Skew | Low |
| Package Type | 52-Pin Thin Quad Flat Package |
No, the CDC586 does not require external RC networks because the loop filter for the PLL is included on the chip.
The FBIN pin is used to synchronize the output clocks in frequency and phase to the CLKIN input.
When the OE pin is high, all outputs are placed in the high-impedance state.