The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of the A input. The propagation delays are adjusted at the factory using the P0 and P1 pins. These pins are not intended for customer use and should be strapped to GND. The CDC341 is characterized for operation from 0°C to 70°C.
The CDC341 is a high-performance clock-driver circuit designed to distribute a single input signal to eight outputs with minimum skew. It utilizes an EPIC-IIB BiCMOS design to significantly reduce power dissipation and includes distributed Vcc and ground pins to minimize switching noise. The device features TTL-compatible inputs and outputs with high-drive capabilities of 48 mA.
| High-Level Output Current | -48 mA |
|---|---|
| Operating Temperature | 0°C to 70°C |
| Package Type | DW Plastic Small-Outline Package |
The device is characterized for operation from 0°C to 70°C.
Yes, through the use of control pins 1G and 2G, the outputs can be placed in a low state regardless of the A input.