The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit wi
The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair to ten differential pairs of clock outputs and one differential pair of feedback clock output. It operates from dual 2.5-V supplies and is compatible with spread spectrum clocking to reduce EMI. The device features three-state outputs when the input differential clocks are below 20 MHz and includes an input frequency detection circuit to manage low-frequency conditions.
| Operating Frequency | 60 to 180 MHz |
|---|---|
| Low Jitter (cyc-cyc) | +50 ps |
| Operating Temperature | 0°C to 85°C |
The device operates from 60 to 180 MHz.
Yes, the device is able to track spread spectrum clocking for reduced EMI.
The outputs switch in phase and frequency with the input clock.