NXP LPC11U6x Manuals

ManualLib has 3 documents for the NXP LPC11U6x (microcontrollers): 1 user manual, 1 datasheet, 1 application note. Every file can be read online or downloaded as a PDF for free.

User Manual 1Datasheet 1Application Note 1

Key facts

Brand
NXP
Model
LPC11U6x
Documents
3
Languages
EN
Last added
2014-05-30

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NXP UM10732 LPC User

NXP UM10732 LPC User

User Manual 605 pages · 3 MB · EN

The LPC11U6x/E6x family is a low-cost 32-bit microcontroller based on the ARM Cortex-M0+ core, operating at frequencies up to 50 MHz. These devices feature up to 256 kB of flash memory, 4 kB of EEPROM, and 36 kB of SRAM, designed for energy-efficient applications.

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NXP LPC11U6x specifications

CPU CoreARM Cortex-M0+
Max CPU Frequency50 MHz
Flash MemoryUp to 256 kB
EEPROM4 kB
SRAM36 kB
ADC Resolution12-bit
ADC Sample Rate2 Msamples/s
Operating Voltage2.4 V to 3.6 V
Operating Temperature-40 °C to +105 °C
GPIO PinsUp to 80

Source: NXP UM10732 LPC User

All NXP LPC11U6x documents by type

User Manual 1

Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.

Datasheet 1

Ratings, dimensions and ordering codes, for selection and design work.

Application Note 1

How to use the product for one specific task, with worked examples.

Questions answered in these manuals

What is the maximum CPU frequency of the LPC11U6x/E6x?

The microcontroller family operates at CPU frequencies of up to 50 MHz.

From: NXP UM10732 LPC User

What is the maximum sample rate of the ADC?

The 12-bit ADC supports sample rates of up to 2 Msamples/s.

From: NXP UM10732 LPC User

What is the maximum CPU frequency for the LPC11U6x microcontroller?

The microcontroller operates at CPU frequencies of up to 50 MHz.

From: NXP LPC11U6x Cortex-M0+ Microcontroller Datasheet

What is the maximum amount of flash memory supported by the LPC11U6x?

The device supports up to 256 kB of flash memory.

From: NXP LPC11U6x Cortex-M0+ Microcontroller Datasheet

Where are the IAP routines located?

The IAP routines are located in the Boot ROM at address Ox1FFF1FF0.

From: NXP AN11511 Electronic components Application

What precautions must be taken regarding interrupts during IAP?

Any access to flash memory must be avoided; if the vector table interrupt is in flash, all interrupts must be disabled prior to erase and write.

From: NXP AN11511 Electronic components Application