This application note describes the In-Application Programming capabilities of LPC11U6X. It also provides guidance to interrupt handling during flash IAP calls.
The document details the In-Application Programming (IAP) features available in the NXP LPC11U6x family, which are ARM Cortex-M0+ based 32-bit MCUs. It covers the manipulation of on-chip flash memory and EEPROM while running user application code.
Key topics include initialization procedures for IAP routines located in the Boot ROM, a comprehensive list of available IAP commands (such as erasing sectors, copying RAM to Flash, and reading device identification), and critical precautions regarding interrupt handling and RAM usage during programming operations.
| CPU Core | ARM Cortex-M0+ |
|---|---|
| Max CPU Frequency | 50 MHz |
| Flash Memory Size | up to 256 kB |
| EEPROM Size | 4 kB |
| SRAM Size | 36 kB |
The IAP routines are located in the Boot ROM at address Ox1FFF1FF0.
Any access to flash memory must be avoided; if the vector table interrupt is in flash, all interrupts must be disabled prior to erase and write.
The IAP routines utilize 32 bytes of space in the top portion of on-chip RAM for execution.