The CDC2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509A operates at 3.3-V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products...
The CDC2509A is a high-performance, low-skew, and low-jitter phase-lock loop (PLL) clock driver operating at 3.3 V. It is specifically designed to distribute one clock input signal to nine outputs: five in one bank and four in another. The device includes an on-chip PLL loop filter, eliminating the need for external RC networks.
| Supply Voltage (Voc) | 3 V to 3.6 V |
|---|---|
| Operating Temperature Range | 0°C to 70°C |
No, it does not require external RC networks because the loop filter is included on-chip.
The device operates at 3.3 V.