The CDC2582 is a high-performance, low-skew, low-jitter clock driver that uses a phase-lock loop (PLL) to precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN, CLKIN) input.
The CDC2582 is a high-performance, low-skew, low-jitter clock driver designed for synchronous DRAMs and clock-generation applications. It utilizes a phase-locked loop (PLL) to align the frequency and phase of output signals to differential LVPECL clock inputs. The device operates at 3.3 V and features internal 26-Ω series resistors to improve signal integrity.
| Operating Temperature | 0°C to 70°C |
|---|---|
| Input Frequency Range | 25 MHz to 100 MHz |
| Package Type | 52-Pin Quad Flatpack |
No, the CDC2582 does not require external RC networks as the loop filter is included on the chip.
A stabilization time is required following power up or changes to the PLL reference or feedback signal to achieve phase lock.