cdc2509b 3.3-v phase-lock loop clock driver is a phase-lock loop clock distributor for synchronous dram applications. it distributes one clock input to one bank of five and one bank of four outputs. each output bank has a separate output enable. the external feedback (fbin) terminal is used to synchronize the outputs to the clock input. cdc2509b operates at 3.3-v vcc. it also provides integrated series damping resistors, making it ideal for driving point-to-point loads.