The CDC2509 is a 3.3V phase-lock loop clock driver that uses a PLL to precisely align the feedback output to the clock input signal in both frequency and phase. This product is specifically designed for use with synchronous DRAM. The CDC2509 operates at 3.3V VCC and provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can be enabled or disabled separately via the control inputs (1G and 2G). When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2509 does not require an external RC network.
The CDC2509 is a high-performance, low-skew, low-jitter phase-lock loop (PLL) clock driver specifically designed for synchronous DRAM applications. It distributes one clock input to nine outputs (one bank of five and one bank of four) with separate output enable controls for each bank. The device operates at 3.3 V and includes on-chip series-damping resistors and a loop filter, eliminating the need for external RC networks.
| Supply Voltage | 3.0 V to 3.6 V |
|---|---|
| Operating Temperature | 0°C to 70°C |
| Clock Frequency | 25 MHz to 125 MHz |
| Stabilization Time | 7 ms |
| Skew (Typical) | 200 ps |
| Jitter (Typical) | 100 ps |
| Package | 24-Pin Thin Shrink Small-Outline Package |
No, the CDC2509 does not require external RC networks because the loop filter for the PLL is included on-chip.
The stabilization time required for the integrated PLL circuit to obtain phase lock is 7 ms.
Yes, the PLL can be bypassed for test purposes by strapping the AVcc pin to ground.