The CDC208 is a dual 1-line to 4-line clock driver designed for clock distribution applications. It features low-skew propagation delay, TTL-compatible inputs, CMOS-compatible outputs, flow-through architecture for optimized PCB layout, center-pin VCC and GND pin configurations to minimize high-speed switching noise, and is manufactured using the EPIC (Enhanced-Performance Implanted CMOS) 1-µm process. The device also offers output-enable inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the input signal.