The CDC208 is a dual 1-line to 4-line clock driver designed for clock distribution applications. It features low-skew propagation delay, TTL-compatible inputs, CMOS-compatible outputs, flow-through architecture for optimized PCB layout, center-pin VCC and GND pin configurations to minimize high-speed switching noise, and is manufactured using the EPIC (Enhanced-Performance Implanted CMOS) 1-µm process. The device also offers output-enable inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the input signal.
The CDC208 is an integrated circuit containing two independent clock-driver circuits. Each circuit takes a single input signal and distributes it to four separate outputs while maintaining minimum skew between them. The device features TTL-compatible inputs and CMOS-compatible outputs, utilizing a flow-through architecture to optimize PCB layout. It includes output-enable controls that allow the outputs to be disabled into a high-impedance state or driven to specific logic levels.
| Operating Temperature Range | -40°C to 85°C |
|---|---|
| Supply Voltage (VCC) | 4.5 V to 5.5 V |
| High-Level Output Current (Ioh) | -24 mA |
| Low-Level Output Current (Iol) | 24 mA |
The CDC208 is a dual clock-driver circuit that fans out one input signal to four outputs with minimum skew for clock distribution.
The device is characterized for operation from -40°C to 85°C.