Key facts
- Brand
- Intel
- Model
- Stratix 10
- Category
- Other Electronics
- Documents
- 3
- Languages
- EN
- Last added
- 2026-10-15
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Intel Stratix 10 HBM2 Interface FPGA IP User Guide
This document serves as a comprehensive user guide for the High Bandwidth Memory (HBM2) Interface Intel FPGA IP core. It provides detailed information on the architecture, features, and parameterization of the interface designed specifically for use with Intel Stratix 10 devices.
The guide covers the creation and configuration of the IP within the Intel Quartus Prime Design Suite, including general parameters, I/O settings, controller configurations, and pin planning. It also details simulation procedures using various tools such as ModelSim, Questa, Synopsys VCS, Riviera-PRO, and Cadence Xcelium.
Intel Stratix 10 specifications
| Maximum HBM2 interfaces supported per device | two |
|---|---|
| Data bus width per channel | 128-bit DDR data bus |
| Supported DRAM densities | 4GB and 8GB |
| Number of independent channels per stack | up to eight channels |
All Intel Stratix 10 documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
How to use the product for one specific task, with worked examples.
Questions answered in these manuals
Which software suite is required for this IP?
The document states it was updated for the Intel Quartus Prime Design Suite version 21.3.
What is the IP version number?
The current release information indicates an IP Version of 19.6.1.
What is the purpose of the Intel FPGA remote temperature sensing diode system?
It allows using third-party chips to monitor the junction temperature (TJ) even while the FPGA is powered down or not configured.
From: AN 769: Intel FPGA Remote Temperature Sensing Diode Implementation Guide
Which FPGA device family does this guide apply to?
It applies to remote TSD implementation for the Intel Stratix® 10 FPGA device family.
From: AN 769: Intel FPGA Remote Temperature Sensing Diode Implementation Guide
What FPGA is used in the Intel Stratix 10 PAC?
The FPGA part number is 1SX280HN2F43E2VGS3.
From: Intel Stratix 10 PAC 4-Channel DDR4 RDIMM Design Manual
What software is required to program the PAC?
Intel Quartus Prime Pro Edition version 18.1 is required.
From: Intel Stratix 10 PAC 4-Channel DDR4 RDIMM Design Manual