Intel Stratix 10 HBM2 Interface FPGA IP User Guide

About this manual

This document serves as a comprehensive user guide for the High Bandwidth Memory (HBM2) Interface Intel FPGA IP core. It provides detailed information on the architecture, features, and parameterization of the interface designed specifically for use with Intel Stratix 10 devices.

The guide covers the creation and configuration of the IP within the Intel Quartus Prime Design Suite, including general parameters, I/O settings, controller configurations, and pin planning. It also details simulation procedures using various tools such as ModelSim, Questa, Synopsys VCS, Riviera-PRO, and Cadence Xcelium.

What's inside

• About the High Bandwidth Memory (HBM2) Interface Intel FPGA IP
• Introduction to High Bandwidth Memory
• Intel Stratix 10 HBM2 Architecture
• Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel FPGA IP
• Pin Planning for the High Bandwidth Memory (HBM2) Interface Intel FPGA IP
• Simulating the High Bandwidth Memory (HBM2) Interface Intel FPGA IP
• High Bandwidth Memory (HBM2) Interface Intel FPGA IP Interface
• User AXI Interface Timing
• High Bandwidth Memory (HBM2) Interface Intel FPGA IP Controller Performance

Specifications

Frequently asked questions

Which software suite is required for this IP?

The document states it was updated for the Intel Quartus Prime Design Suite version 21.3.

What is the IP version number?

The current release information indicates an IP Version of 19.6.1.