K4S561633C-R(B)L/N/P is a 4M x 16Bit x 4 Banks Synchronous DRAM launched by Samsung. It adopts 54CSP package and supports 3.0V/3.0V and 3.3V/3.3V two power supply voltages. The chip has four banks operation, MRS cycle, address key program, delay cycle, burst length and burst type functions, and supports auto refresh.
The document provides a detailed description of the K4S561633C-R(B)L/N/P CMOS SDRAM, a 4M × 16‑bit synchronous DRAM organized in four banks and packaged in a 54‑ball CSP. It lists features such as 3.0 V/3.3 V operation, selectable CAS latency, and various burst lengths.
Key sections include functional block diagrams, pin configurations, absolute maximum ratings, DC and AC operating conditions, and timing parameters. The data sheet also contains ordering information, package dimensions, and a simplified truth table for command encoding.
| Data organization | 4M × 16 bits (16 Mx 16) |
|---|---|
| Package type | 54‑ball CSP |
| Supply voltage (VDD) | 2.7 V – 3.6 V |
| Power dissipation | 1 W |
| Storage temperature range | -55 °C – +150 °C |
| CAS latency options | 1, 2, 3 |
| Burst length options | 1, 2, 4, 8, Full page |
| Operating frequency (typical) | 105 MHz (GL=2) |
The recommended supply voltage is 2.7 V to 3.6 V.
The device supports CAS latency values of 1, 2, or 3.
The package uses a 54‑ball CSP layout.