This handbook provides data sheet specifications for the Cyclone® FPGA family, including information on internal architecture, configuration and JTAG boundary-scan testing, DC operating conditions, AC timing parameters, power consumption, and ordering information.
This document provides preliminary data sheet specifications for the Cyclone FPGA family. It details the internal architecture, including Logic Array Blocks (LABs), Logic Elements (LEs), and embedded memory blocks. The guide also covers configuration and testing methods, DC and switching characteristics, power consumption references, and ordering information for various device densities.
| Logic Elements (LEs) | 2,910 to 20,060 |
|---|---|
| Embedded RAM | up to 288 Kbits |
| LVDS Data Rate | up to 640 Mbps |
| PCI Support | 66- and 33-MHz, 64- and 32-bit |
| Process Technology | 1.5-V, 0.13-μm |
Cyclone devices range between 2,910 to 20,060 logic elements (LEs).
They support LVTTL, LVCMOS, SSTL-2, SSTL-3, LVDS, RSDS, and PCI standards.
Up to two PLLs per device provide clock multiplication and phase shifting.